Advanced Packaging

Vacuum Deposition Equipment for Wafer- or Panel-Level Substrates

There are ma­ny ap­proach­es to ad­vanced sem­i­con­duc­tor packag­ing, the art of ef­fi­cient­ly and com­pact­ly con­nect­ing mul­ti­ple chips to max­i­mize sys­tem per­for­mance.

In­creas­ing­ly com­plex e­lec­tri­cal sys­tems are cre­at­ed by ad­vanced packag­ing ap­proach­es. As a re­sult, the re­quire­ments for the con­duc­tive and in­su­la­t­ing lay­ers are be­com­ing more com­plex. At the same time, the sub­strates and the ut­i­liz­a­tion of the avail­able ar­ea must be op­timized to man­u­fac­ture these de­vices cost-effec­tive­ly.

Ma­te­ri­als, and the pro­cess­es used to de­pos­it them, are in­creas­ing­ly com­plex, de­mand­ing high­ly en­gi­neered plat­forms that can solve the most com­plex met­al­li­za­tion chal­leng­es for high-aspect-ratio struc­tures. And this is where we ex­cel: in­no­va­tion in ma­te­ri­als and e­quip­ment, on wafer or panel sub­strates, with sub-nanome­ter pre­ci­sion.