For decades, the semiconductor industry has pursued a clear objective: to integrate as many functions as possible into a single system-on-chip (SoC). By scaling transistors from millions to trillions on a single die, the “More Moore” large-scale integration approach delivered remarkable technical and economic benefits, leading to technologies that enabled the PC, mobile phone, and the early stages of artificial intelligence (AI).
Over time, it became obvious that not all functions on the SoC benefit from scaling in the same way. New megatrends require optimization on all fronts: the compute cores, memory subsystems, interfaces, as well as the power supply infrastructure.
Today this shift is most visible in high-performance compute, where we are witnessing a de-integration of monolithic SoCs and replacing them with heterogeneous, chiplet-based architectures. Functions that were once distributed across printed circuit boards and discrete packages are now brought into close proximity within a single advanced package to deliver higher bandwidth, lower latency, improved power efficiency and better cost control. “More than Moore”— value created by integrating diverse functions and technologies into a single package—has been critical to the performance and cost efficiencies that enable AI to scale today.
In 2026, we expect to see this architectural transition expand beyond compute. High-end radio frequency (RF) components will be co-packaged with data processing companion chips, similar to what we have been doing for decades with camera and image sensor solutions. Similarly, we will see power semiconductors being integrated with logic chips for better efficiency and system response. Photonic integrated circuits (PICs) will be packaged together with data processing chips to overcome electrical interconnect limits for better signal integrity.
Of course, economics need to benefit as well. The industry transitioned from wafer-level packaging to panel-level packaging to improve cost-efficiency. Similarly, heterogeneous integration offers an opportunity to combine chips from different wafer sizes and technology nodes and place them as close together as possible within a single package to maximize performance and yield.
VON ARDENNE’s equipment portfolio is well positioned to support these advanced packaging roadmaps in 2026 and beyond. From cluster-based systems for wafer-level packaging, to panel-level equipment for larger package formats—VON ARDENNE enables high throughput, uniform, and scalable deposition and processing. These solutions support the ability to create and fill nanometer-level structures, regardless of substrate size or type, ensuring flexibility and quality as packaging architectures continue to evolve.
Guido Ueberreiter, VP Semiconductor Strategy, VON ARDENNE